Title:
【発明の名称】データフォーマット変換器
Document Type and Number:
Japanese Patent JP2985560
Kind Code:
B2
Abstract:
PURPOSE:To simplify a processing at a processing part of the succeeding stage by preventing the data of each frame from being mixed, and outputting a pulse indicating leading together with the pulse indicating invalid data. CONSTITUTION:A serial signal obtained by making a frame having (2N+1) pieces of the data of A bit width in which the (2M+1)th (N>M) data are invalid data serial is inputted to a first serial/parallel converter 1, and a a parallel signal in which the signals of a first column and the signals of a second column become successively parallel by A bit width units is obtd. The signals of the first column are inputted to an FF3, selector 12, FF4, and selector 11, and the signals of the second column are inputted through an FF5 and an FF6 to selectors 11 and 12. The pulse indicating the leading of the frame is inputted to a second serial/parallel converter 2, and the pulse indicating the leading of each parallel signals of the odd numbered frame and the even numbered frame is obtained, and outputted through FF7-10 to the processing part of the succeeding stage, and inputted to a control part 20. Then, the parallel signal in which the data of each frame are not mixed, and the pulse indicating the leading and the pulse indicating the invalid data are outputted to the processing part of the succeeding stage.
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Inventors:
WATANABE TOMOHARU
TAKIZAWA JUJI
TAKIZAWA JUJI
Application Number:
JP6072293A
Publication Date:
December 06, 1999
Filing Date:
March 19, 1993
Export Citation:
Assignee:
FUJITSU KK
International Classes:
H03M9/00; H04L13/10; H04L29/06; (IPC1-7): H04L29/06
Attorney, Agent or Firm:
Teiichi