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Title:
MANUFACTURE OF MOS INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS586171
Kind Code:
A
Abstract:

PURPOSE: To obtain favorable contact of wiring of an MOS integrated circuit device by a method wherein after an Si substrate is made to expose at the region to form direct contact, a high melting point metal oxide layer is formed only at the place thereof, the Si substrate under the layer thereof is doped with impurities, and the directly contacting high melting point metal gate wiring is applied thereto.

CONSTITUTION: After field oxide films 12 is formed on the Si substrate 11, a gate oxide film 13 is formed on the active region, and an Si3N4 film 14 is formed on the whole surface. After the Si surface 15 to form direct contact is exposed, a film is formed on the whole surface using a high melting point metal material (Mo), then As ions are implanted, and the N+ type Si region 17 doped with high concentration As is formed in the exposed Si surface. After the heat treatment is performed, Mo at the non reacted part is removed, and the Mo3Si layer 18 is formed only on the surface of the N+ type Si region. Then the heat treatment is performed in the N2 gas atmosphere, and the silicide 18 is converted into the MoSi layer 19 of the tetragonal system. Then Mo is evaporated by sputtering, and after the Mo gate wiring 20 is formed coming in contact with a part of the surface of the layer 19, the heat treatment is performed at the temperature of 500∼800°C in gas containing H2 and N2.


Inventors:
NAGASAWA EIJI
HIGUCHI KOUHEI
MORIMOTO MITSUTAKA
OKABAYASHI HIDEKAZU
Application Number:
JP10354781A
Publication Date:
January 13, 1983
Filing Date:
July 02, 1981
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L21/28; H01L21/768; H01L29/78; (IPC1-7): H01L21/88; H01L29/62
Attorney, Agent or Firm:
Uchihara Shin



 
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