PURPOSE: To reduce the area of a semiconductor device in which there are formed on the same substrate a bipolar transistor operable in an analog manner and a logic circuit, and further reduce the number of fabrication processes of the semiconductor device.

CONSTITUTION: There are formed an nSIT 2, a D-type p- MIS transistor 5, and an E-type pMOS transistor 6 on a p type semiconductor substrate 1. In a fabrication process of the semiconductor device, there are simultaneosuly formed a p+ type gate region 15A of the nSIT2, and p+ type source regions 15D, 15E and p" type drain regions 15D', 15E' of the MOS transistors 5, 6 and further there are simultaneously formed a source polysilicon electrode 18A of the nSIT2 and gate electrodes 18D, 18E of the MOS transistors 5, 6.