PURPOSE: To execute complicated arithmetic operation or a transfer instruction at a high-speed and with a small-capacity microgram by providing a flag for showing the end of arithmetic operation, data valid register for instructing the number of valid data in fraction byte data, and circuit for controlling the data valid register.
CONSTITUTION: A data valid register 9-0 is provided with N pieces of valid/ invalid showing whether n-byte data are valid or invalid corresponding to a read buffer 4-0 composed of N bytes, and end flag showing the end of read counting. A data valid register control circuit 8-0 generates data to be written in the data valid register 9-0 based number of bytes of memory data to be written in a read counter 7-0 and a read buffer 4-0 and subtracts the contents of the read counter 7-0 just by the number of bytes at the time of next memory read.
| JPH01180635 | PROCESSOR CONSTITUTING SYSTEM |
| JP3634292 | FUNCTION OPERAND DIVISION TYPE PROCESSOR |
| WO/2019/202288 | TRACKING SPECULATIVE DATA CACHING |
ARAKI SATORU
SHIMADA YOSHIHIKO
YOSHIDA SHIGERU
SUGINO KAZUHITO
MATSUBARA NOZOMI
