Title:
【発明の名称】符号化装置
Document Type and Number:
Japanese Patent JP3316313
Kind Code:
B2
Abstract:
An encoder includes a control bit insertion circuit (12) for inserting a control bit into input data, which is then subjected to I-NRZ modulation by a precoder (14) to generate a reference code. The reference code is given to a 4-code generation circuit (22) through a delay circuit (16), and frequency components of the reference code, and first, second and third codes generated on the basis of the reference code are detected by a frequency detector (18). The frequency components are given to a judge circuit (20) such that it is determined whether the frequency components are large or small. A judge signal is applied to the 4-code generation circuit and a frequency detector from the judge circuit. The 4-code generation circuit selectively outputs one selected from the reference code and the first to third codes on the basis of the judgement signal.
Inventors:
Akira Sotoguchi
Application Number:
JP23259394A
Publication Date:
August 19, 2002
Filing Date:
September 28, 1994
Export Citation:
Assignee:
Sanyo Electric Co., Ltd.
International Classes:
G11B5/008; G11B5/09; G11B15/46; G11B20/14; H03M5/06; H03M5/14; (IPC1-7): G11B20/14; H03M5/06
Domestic Patent References:
| JP6236536A | ||||
| JP4255969A | ||||
| JP595291A |
Attorney, Agent or Firm:
Yoshito Yamada