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Title:
PREPARATION OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS5853863
Kind Code:
A
Abstract:

PURPOSE: To obtain an FET in high electron mobility by providing the n-Al GaAsP layer through the buffer layer on the non-additive AlGaAsP layer and by selectively irradiating the proton to the source/drain regions while the substrate is kept at a temperature of 550°C.

CONSTITUTION: The i-GaAs2, i-AlGaAsP3, Si-added n-AlGaAsP4 are stacked by the molecular beam epitaxial method on the Cr-added semi-insulating GaAs substrate 1, and then the protection film AlN5 is provided by the reactive sputtering method. The SiO2 mask providing an aperture is formed over the source/drain regions 6,7. The substrate as a whole is kept at about 650°C and then the proton is implanted into the layer 4. Thereby, excessive cavities are generated and new additive regions 9, 10 are generated through acceleration of diffusion of Si. The layer 5 is removed by etching from the regions 7, 8 and the Au/AuGe 11 are evaporated and then it is sintered. Thereafter, the layer 6 and the upper layer 11 are removed by etching and the Al gate electrode 12 is formed. According to this structure, diffusion to the channel layer 2 from the electron suply layer 4 is prevented, the electron mobility is not deteriorated, souce/drain contact resistance is also not degraded and an FET having excellent characteristic can be obtained.


Inventors:
NISHI HIDETOSHI
ISHIKAWA TOMONORI
Application Number:
JP15268481A
Publication Date:
March 30, 1983
Filing Date:
September 26, 1981
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L21/265; H01L21/338; H01L29/51; H01L29/778; H01L29/80; H01L29/812; (IPC1-7): H01L21/265
Attorney, Agent or Firm:
Koshiro Matsuoka