Title:
【発明の名称】折り返し及び間引きフィルタアーキテクチャ
Document Type and Number:
Japanese Patent JPH07500461
Kind Code:
A
Abstract:
Decimation circuitry having a forward shifting data section receiving data samples in order including a plurality of forward decimation registers coupled in-line and providing a forward register output. Each forward decimation register operates as a first-in-first-out (FIFO) register having a decimation depth. A backward shifting data section includes a plurality of backward decimation registers having a decimation depth coupled in-line and providing a backward register output. One of the backward decimation registers which receives data samples in sequence from one of the forward decimation registers can function as both a last-in-first-out (LIFO) and a FIFO register, when a LIFO register, it operates to reverse blocks of data samples wherein the size of each block corresponds to the decimation rate. Each reversed block is then shifted through the backward shifting data section. Each of the other backward decimation registers operates as FIFO register. The decimation circuitry can be used to form a digital filter cascadable into various sizes.
Inventors:
John Stone, William, Franklin
Damello, david, henry
Damello, david, henry
Application Number:
JP50724292A
Publication Date:
January 12, 1995
Filing Date:
October 13, 1992
Export Citation:
Assignee:
Harris Corporation
International Classes:
H03H17/00; H03H17/02; H03H17/06; (IPC1-7): H03H17/02; H03H17/06
Attorney, Agent or Firm:
Tadahiko Ito (1 outside)