Title:
COMPUTER SYSTEM
Document Type and Number:
Japanese Patent JPH0635873
Kind Code:
A
Abstract:
PURPOSE: To incorporate parallel array processors on a single semiconductor silicon chip.
CONSTITUTION: The parallel array processors for large scaled parallel application are formed by low output CMOS provided with a DRAM processing mechanism and processing elements are incorporated on a single chip. The eight processors on the single chip have the processing elements connected to themselves, large scaled memories and input/output mechanisms and they are connected by a corrected topology based on a hypercube. Nodes are connected by a hypercube network topology, a corrected hypercube network topology, a ring network topology or an intra-ring network topology.
Inventors:
TOMASU NOOMAN BAAKAA
KURAIBU ARAN KORINZU
MAIKERU CHIYAARUZU DATSUPU
JIEEMUZU UOREN DEIIFUENDERUFUA
BIRII JIYATSUKU NOURUZU
DONARUDO MAIKERU RESUMAISUTAA
RICHIYAADO AANESUTO MAIRUZU
RICHIYAADO EDOWAADO NAIYAA
ROBAATO RAISUTO RICHIYAADOSON
DEEBUITSUDO BURUUSU RORUFU
BUINSENTO JIYON SUMOORARU
KURAIBU ARAN KORINZU
MAIKERU CHIYAARUZU DATSUPU
JIEEMUZU UOREN DEIIFUENDERUFUA
BIRII JIYATSUKU NOURUZU
DONARUDO MAIKERU RESUMAISUTAA
RICHIYAADO AANESUTO MAIRUZU
RICHIYAADO EDOWAADO NAIYAA
ROBAATO RAISUTO RICHIYAADOSON
DEEBUITSUDO BURUUSU RORUFU
BUINSENTO JIYON SUMOORARU
Application Number:
JP10963193A
Publication Date:
February 10, 1994
Filing Date:
May 11, 1993
Export Citation:
Assignee:
IBM
International Classes:
G06F15/173; G06F15/16; G06F15/80; (IPC1-7): G06F15/16
Domestic Patent References:
| JPH01127048U | 1989-08-30 |
Attorney, Agent or Firm:
Koichi Tonmiya (4 outside)