Title:
【発明の名称】改良形復号器回路
Document Type and Number:
Japanese Patent JP2922297
Kind Code:
B2
Abstract:
An improved decoder circuit suitable for decoding an encoded binary data stream. The encoding is expected to generate a three-part code format, the format, in turn, comprising a pair of clock transitions that set-off a data transition. The improved decoder circuit establishes whether or not the expected format is in fact realized under arbitrary operating conditions, and in the event of a failure to realize the expected format, provides a suitable format for a subsequent decoding procedure.
Inventors:
SHIRUBA FUERUNANDO GONKARUBESU
Application Number:
JP51253490A
Publication Date:
July 19, 1999
Filing Date:
August 23, 1990
Export Citation:
Assignee:
IISUTOMAN KODATSUKU CO
International Classes:
H03M5/02; H03M5/12; G11B20/14; H03M5/14; (IPC1-7): H03M5/02
Domestic Patent References:
| JP60144051A | ||||
| JP52116222A | ||||
| JP4503895A | ||||
| JP4504338A |
Attorney, Agent or Firm:
Takashi Ishida (3 others)