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Title:
INFORMATION PROCESSING DEVICE
Document Type and Number:
Japanese Patent JPS5942683
Kind Code:
A
Abstract:

PURPOSE: To clear a cache memory at a time, when the normal execution of a program is not hindered, and before the access of a shared area, by providing a flip flop for storing an error and storing the error of a common line because of which clearing for every entry is impossible.

CONSTITUTION: If a parity error is detected on a zone/command line 16 by a parity checker 31 when a line ZFSTCM 17 is "1" or a parity error is detected on an address/data line 15 by a parity checker 32 when the line 17 is "1" and a command to update contents of a main storage exists, a flip-flop F/F2 33 is set. When firmware checks a gate word to judge that the access to the shared area is permitted, it checks the state of the flip-flop F/F2 33; and if this flip flop F/F2 is set, all entries whose contents do not coincide with contents of the main storage probably are cleared, and the flip flop F/F2 33 is reset.


Inventors:
SUZUKI SHIYOUHEI
SAKAUCHI AKIRA
Application Number:
JP15071582A
Publication Date:
March 09, 1984
Filing Date:
September 01, 1982
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
G06F11/10; G06F12/08; (IPC1-7): G06F13/00
Domestic Patent References:
JPS52149039A1977-12-10
Attorney, Agent or Firm:
Norio Ohu