Title:
【発明の名称】入力レベル試験回路
Document Type and Number:
Japanese Patent JP2671832
Kind Code:
B2
Abstract:
PURPOSE: To enable a test to be performed without receiving the effect of noise due to the operation of an internal circuit by inputting a control signal controlling a test mode and a usual operation mode to both of an input buffer circuit and an output buffer circuit. CONSTITUTION: In a usual operation mode, a control signal input terminal 100 is set high and all of the transistors 1, 4 of input buffer circuits 200, 201 and the transistors 6, 11 of output buffer circuits 202, 203 are set to a non-continuity state. The output signal of an internal circuit 19 is outputted to pads 16, 17 through the output buffer circuits 202, 203. Next, at the time of a test mode, the input terminal 100 is set low and all of the transistors 6, 11 of the output buffer circuits 202, 203 and the transistors 1, 4 of the input buffer circuits 200, 201 are set to a continuity state. That is, the logical signals corresponding to the signal levels of the input buffer circuits 200, 201 are outputted to the output buffer circuits 202, 203 and the test of an input level can be performed without relying on the output of the internal circuit 19.
Inventors:
Hidekatsu Masuko
Application Number:
JP27422794A
Publication Date:
November 05, 1997
Filing Date:
October 14, 1994
Export Citation:
Assignee:
NEC
International Classes:
G06F11/22; H01L21/66; H01L21/822; H01L27/04; G01R31/28; (IPC1-7): G01R31/28; G06F11/22; H01L21/66; H01L21/822; H01L27/04
Domestic Patent References:
| JP277667A | ||||
| JP6138576A | ||||
| JP611547A | ||||
| JP843492A | ||||
| JP5256910A | ||||
| JP5243361A | ||||
| JP495885A | ||||
| JP3144385A | ||||
| JP526981A |
Attorney, Agent or Firm:
Asato Kato