Title:
【発明の名称】検査回路
Document Type and Number:
Japanese Patent JP2917852
Kind Code:
B2
Abstract:
PURPOSE: To obtain an inspection circuit in which high speed inspection is realized by embedding a circuit for converting a low speed signal into a high speed signal in an LSI. CONSTITUTION: The inspection circuit comprises oscillation circuits 12, 13 for counting the duration of the signal value '1' or '0' of low speed clock using a high speed clock signal running freely in the oscillation circuit and stopping oscillation of the high speed clock when a predetermined count is reached. Logical sum of the outputs from the oscillation circuits 12, 13 is used, as a high speed clock, in an integrated circuit and a low speed data from a tester 101 is fed through a parallel/serial conversion circuit 17 to the integrated circuit. Output from the integrated circuit is delivered through a seria/parallel conversion circuit 16 to the tester 101.
Inventors:
WAKAYAMA YASUSHI
Application Number:
JP7511095A
Publication Date:
July 12, 1999
Filing Date:
March 31, 1995
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G01R31/3183; G06F1/04; G06F15/78; G01R31/28; (IPC1-7): G01R31/3183; G01R31/28; G06F1/04; G06F15/78
Domestic Patent References:
| JP6187797A | ||||
| JP6242188A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)