PURPOSE: To prevent the monotony of an output current from being spoiled when a digital input varies, by providing a current mirror circuit with a holding gate between the output terminal of a DA converter and a power source.

CONSTITUTION: A current mirror circuit 40 provided with a holding gate is provided between the terminal 36 of a DA converter 6 and the terminal 37 of a power source VD2. When a clock signal synchronizing with a digital input to the gate of the transfor MOSFET42 of the circuit 40 has a high level, an FET42 turns on to short the gates of FETs 41 and 43, and the circuit 40 becomes equivalent to a current mirror circuit. When the FETs 41 and 43 are equalized in gm, equal currents flow through the FETs 41 and 43. When the signal has a low level and the FET42 still turns off, the gate potential of the FET43 is unchanged because of charges accumulated in a capacitance 44, and the same current flows continuously. Therefore, even if the digital input varies and the output current I1 of the converter 6 decreases temporarily and increases to a high value, the output current flowing to the drain of the FET43 has no abnormal waveform, thus obtaining the monotony.