Title:
【発明の名称】インバータ回路
Document Type and Number:
Japanese Patent JP2568636
Kind Code:
B2
Abstract:
PURPOSE:To prevent malfunction of an internal circuit due to glitch by suppressing a peak value of a through current flowing to ground via P and N-channel transistors(TRs) at the time of switching and that of a discharge current flowing from an external load to ground via an N-channel TR. CONSTITUTION:Plural N-channel TRs Tn1, Tn2 are connected in parallel between the drain of a P-channel TR Tp and ground. An input signal is supplied to the gate of the N-channel TR of the frontmost stage of the plural N-channel TRs and source terminals of each N-channel TR are connected via a resistor except that of the N-channel TR of the final stage. Then gate terminals of the N-channel TRs are connected to the source of the N-channel TR of the pre-stage. Thus, the peak value of the through-current and discharge current flowing to ground is suppressed and the production of glitch is prevented in advance.
Inventors:
Inagaki Yasunori
Hitoshi Ogawa
Hitoshi Ogawa
Application Number:
JP16293988A
Publication Date:
January 08, 1997
Filing Date:
June 30, 1988
Export Citation:
Assignee:
富士通株式会社
富士通ヴィエルエスアイ株式会社
富士通ヴィエルエスアイ株式会社
International Classes:
H03K17/16; H03K19/003; H03K19/0948; (IPC1-7): H03K19/0948; H03K17/16
Attorney, Agent or Firm:
Teiichi Ijiba (2 outside)