Title:
PARITY BIT GENERATION SYSTEM
Document Type and Number:
Japanese Patent JPS5852754
Kind Code:
A
Abstract:
PURPOSE: To reduce necessary memory areas and the mean number of processing steps, by performing parity adding processing only through bit operation.
CONSTITUTION: Input data a0Wa7 each consisting of plural bits are divided into high-order and low-order digit sides respectively, and exclusive OR of every two bits of the divided data is the same sequence are derived to decide on whether exclusive OR outputs b0Wb3 are all go to 0 or not. When 0 is not derived, the outputs b0Wb3 are divided into two respectively as well as the input data, and they are ORed exclusively and repeatedly to decide on parity bits according to whether outputs C0WC1 of each stage go to 0 or not.
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Inventors:
HARADA KIYOUKO
NAKAGAWA AKIKAZU
YOSHITOME MASAMI
NAKAGAWA AKIKAZU
YOSHITOME MASAMI
Application Number:
JP15105381A
Publication Date:
March 29, 1983
Filing Date:
September 24, 1981
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H03M13/00; G06F11/10; (IPC1-7): G06F11/10
Attorney, Agent or Firm:
Minoru Aoyagi