Title:
【発明の名称】回路内蔵受光素子
Document Type and Number:
Japanese Patent JP2672887
Kind Code:
B2
Abstract:
PURPOSE:To easily remove optical sensitivity abnormal product and a responding speed abnormal product of a circuit containing photodetector in a wafer test by providing a test device for measuring a punch-through resistance and means for applying a reverse bias. CONSTITUTION:An N-type epitaxial layer 7 is laminated on a P-type semiconductor substrate 1, a P-type diffused layer 8, etc., is provided on the layer 7, and a test device 16 is formed. In this case, the thickness of the layer 7 is the same as that of the epitaxial layer of a circuit containing photodetector to be tested for its optical sensitivity and its responding speed, and the device 16 is formed in the same structure as a substrate P-N-P transistor to be normally used in a bipolar IC. Accordingly, since an intrinsic correlation is provided between the punchthrough resistance between the layer 8 and the substrate 1 and the thickness of the layer 7, the optical sensitivity and the optical speed can be indirectly tested by measuring the punchthrough resistance of the device 16. Further, the optical sensitivity and responding speed abnormal products of the photodetector can be easily removed by measuring the punch-through resistance by applying a reverse bias between the layers 8 and 7.
Inventors:
Motohiko Yamamoto
Yokogawa Seiichi
Yokogawa Seiichi
Application Number:
JP28027890A
Publication Date:
November 05, 1997
Filing Date:
October 17, 1990
Export Citation:
Assignee:
Sharp Corporation
International Classes:
H01L31/10; H01L27/14; (IPC1-7): H01L31/10; H01L27/14
Domestic Patent References:
| JP5459890A | ||||
| JP1107118A |
Attorney, Agent or Firm:
Umeda Masaru (2 outside)