Title:
【発明の名称】マッチドフィルタ回路
Document Type and Number:
Japanese Patent JP2926651
Kind Code:
B2
Abstract:
The present invention has an object to provide a matched filter circuit which is possible to synchronize a spreading code with an input signal. A matched filter according to the present invention samples input signal in response to three clocks from the first to the third shifted by a half cycle of a sampling signal so as to judge whether the sampling clock is ahead or behind of the input signal according to signs of input signal sampled. One clock is selected to be the sampling clock.
Inventors:
KOTOBUKI KOKURYO
SHU NAGAAKI
YAMAMOTO MAKOTO
TAKATORI SUNAO
SAWAHASHI MAMORU
ADACHI FUMYUKI
SHU NAGAAKI
YAMAMOTO MAKOTO
TAKATORI SUNAO
SAWAHASHI MAMORU
ADACHI FUMYUKI
Application Number:
JP31002195A
Publication Date:
July 28, 1999
Filing Date:
November 02, 1995
Export Citation:
Assignee:
TAKASAN KK
ENU TEI TEI IDO TSUSHINMO KK
ENU TEI TEI IDO TSUSHINMO KK
International Classes:
H03H15/00; H03H17/02; H04B1/7093; H04J13/00; (IPC1-7): H04J13/00; H03H15/00; H03H17/02
Domestic Patent References:
| JP604341A | ||||
| JP6490634A | ||||
| JP2228142A | ||||
| JP2226826A | ||||
| JP3107228A |
Attorney, Agent or Firm:
Yamamoto Makoto