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Patent Searching and Data


Title:
MEMORY TESTING METHOD
Document Type and Number:
Japanese Patent JPH0737399
Kind Code:
A
Abstract:

PURPOSE: To enhance an efficiency of a memory test and to shorten a testing time by setting a voltage to be applied to a memory to be tested to a specific level or lower, extracting a bit to become defective first and using an address of the defective bit as a base address.

CONSTITUTION: A specified voltage is applied to a memory 21 in a state that the memory 21 to be tested is connected to a terminal of a memory tester. Then, '0' or '1' is written in all bits of the memory 21, read after a predetermined time has elapsed, and checked. Thus, whether there is a bit inversion in written data or not can be checked. If there is no defective bit as a result of the check, a memory voltage is lowered, and this process is repeated. If there is the defective bit, a defective address is stored, and a process is repeated for an inverted pattern. When the inverted pattern is all tested, a test starting address is set to the defective address, and various tests are conducted. Thus, an efficient memory test can be executed to shorten a testing time.


Inventors:
MATSUI NORIYUKI
Application Number:
JP31915591A
Publication Date:
February 07, 1995
Filing Date:
December 03, 1991
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G11C29/00; G11C29/44; (IPC1-7): G11C29/00
Attorney, Agent or Firm:
Akira Yamatani (1 person outside)