Title:
SELECTION CONTROLLER FOR PROCESSOR ARRAY
Document Type and Number:
Japanese Patent JPH06103249
Kind Code:
A
Abstract:
PURPOSE: To simply increase selection of local areas in a processor array.
CONSTITUTION: The identification(ID) number (address) of each processor element 3 in the processor array is given by an alternate binary code and an address mask corresponding to the alternate binary address is generated to select a local area. When the address of a processor element 3 is previously given by a normal binary code, the address is converted into an alternate binary code and a local area is selected by an address mask corresponding to the converted alternate binary address. Thereby, a local area capable of controlling the selection only by one address mask data can be finely set up.
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Inventors:
NAKANISHI MAMORU
OGURA TAKESHI
FUJINO YUICHI
OGURA TAKESHI
FUJINO YUICHI
Application Number:
JP25293792A
Publication Date:
April 15, 1994
Filing Date:
September 22, 1992
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G06F15/16; G06F15/177; G06F15/80; (IPC1-7): G06F15/16
Attorney, Agent or Firm:
Hidekazu Miyoshi (1 outside)