Title:
【発明の名称】マルチプロセツサ処理方式
Document Type and Number:
Japanese Patent JPS5835294
Kind Code:
B2
Abstract:
PURPOSE:To improve processing capacity by providing first-in first-out register groups storing data of predefined fixed lengths between respectively independent processors, and accumulating the processing requests between the processors into the register groups. CONSTITUTION:Plural processors PA, PB and storages MEM-A, MEM-B are connected to system buses BUS-A, BUS-B, whereby the multiprocessor processing system is constituted. First-in first-out register groups FIFO-1, FIFO-2 are connected via an interrupt control circuit INTC between these processors PA and PB, and the respective register groups FIFO-1, FIFO-2 are connected to the BUS-A, BUS-B. The processing requests from the respective processor PA or PB are written in the register group FIFO-1 or FIFO-2, and the respective processing requests are detected through the control circuit INTC, thereafter the contents of the processing requests are read into the processor PB or PA on the other side, whereby the processing capacity is improved.
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Inventors:
NAKAMURA TAKASHI
DOI YASUO
SHIMOMURA FUMIO
HIRAIDE TOSHIHIKO
NAGAFUKU KATSUTERU
DOI YASUO
SHIMOMURA FUMIO
HIRAIDE TOSHIHIKO
NAGAFUKU KATSUTERU
Application Number:
JP1328180A
Publication Date:
August 02, 1983
Filing Date:
February 06, 1980
Export Citation:
Assignee:
FUJITSU KK
NIPPON DENSHIN DENWA KOSHA
NIPPON DENKI KK
HITACHI SEISAKUSHO KK
NIPPON DENSHIN DENWA KOSHA
NIPPON DENKI KK
HITACHI SEISAKUSHO KK
International Classes:
H03M9/00; G06F5/06; G06F13/00; G06F13/38; G06F15/16; G06F15/167; (IPC1-7): G06F15/16
Attorney, Agent or Firm:
Koshiro Matsuoka