Title:
【発明の名称】パラレル/シリアル変換回路
Document Type and Number:
Japanese Patent JP2930083
Kind Code:
B2
Abstract:
PURPOSE:To provide a latch circuit latching parallel data and to convert the parallel data into serial data without fail even when it is generated in arbitrary time. CONSTITUTION:A latch circuit 19 is provided in the front stage of a P/S conversion part 18, and the parallel data generated instantly can be converted into serial data without fail when this latch output is loaded to the conversion part 18. In this case, the conversion part 18 is equipped with a conversion part 18 converting the loaded parallel data into serial data and a load signal generation circuit generating a load signal deciding the load timing to the conversion part 18 for each prescribed time. When the parallel data is inputted to the circuit 19, its rising makes the output of a D-type FF to 'H' and it is sent to the conversion part 18. Then, even when parallel data is generated in arbitrary timing, it can be loaded to the conversion part 18 without fail and converted into serial data without fail.
Inventors:
HIGAKI YOSHIBUMI
Application Number:
JP16882391A
Publication Date:
August 03, 1999
Filing Date:
June 13, 1991
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
H03M9/00; H04L13/10; (IPC1-7): H03M9/00; H04L13/10
Domestic Patent References:
| JP4307834A | ||||
| JP63169128A | ||||
| JP63141415A | ||||
| JP2137133U |
Attorney, Agent or Firm:
Yanagi Kawa Shin