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Title:
【発明の名称】仮想FIFOによる周辺装置インタフェースのシステム並びに方法
Document Type and Number:
Japanese Patent JP3431149
Kind Code:
B2
Abstract:
A system and method for queuing, control and transfer of data between a host processor and a peripheral processor using an architecture and a data flow strategy of one or more virtual FIFO data structures stored in main memory and a hardware FIFO under control of the host and peripheral processors. One virtual FIFO at a time drives the data FIFO with data. In turn, the data FIFO drives a peripheral device with this data. The host software running on the digital processor controls the loading of data for each process (context) into its associated virtual FIFO. The host processor controls the operation of the peripheral processor and the virtual FIFOs. The peripheral processor controls the flow of data from the data FIFO to the peripheral device, and under control of the host software, the flow of data from the driving virtual FIFO to the data FIFO. Start and end address pointers for each virtual FIFO stored in associated memory block indicate the memory location in the virtual FIFO where data is stored. The peripheral processor also keeps a start address pointer of the memory location of the last unused data then read out of the data FIFO to the peripheral device. These address pointers allow the hardware FIFO to be flushed when a context switch occurs, which can take place before all of the data in the driving virtual FIFO is supplied to the data FIFO, and supplied by the data FIFO to the peripheral device.

Inventors:
Lenz, Derek Jay
Application Number:
JP51729293A
Publication Date:
July 28, 2003
Filing Date:
March 26, 1993
Export Citation:
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Assignee:
Seiko Epson Corporation
International Classes:
G06F5/06; G06F13/12; G06F13/28; (IPC1-7): G06F5/06
Domestic Patent References:
JP4290150A
JP2272666A
JP6220041A
JP5994127A
JP62276633A
JP4299389A
JP4275662A
JP4143849A
JP2284235A
JP6352240A
JP60183665A
JP60175165A
JP56108121A
JP5624651A
Attorney, Agent or Firm:
Ryuyoshi Abe (9 outside)