Title:
REAL TIME CORRELATING DEVICE
Document Type and Number:
Japanese Patent JPS5952376
Kind Code:
A
Abstract:
PURPOSE:To double efficiency of use of a hardware and increase processing speed by performing processing of items of orders of even numbers and items of orders of odd numbers separately. CONSTITUTION:An input signal x0 is supplied to a basic circuit 2-0 of an even number item processing circuit 10 and a basic circuit 2-1 of an odd number item processing circuit 11 by the first clock T1. By the second clock T2, the input signal x0 is transferred to basic circuit 2-2 and 2-3, and succeeding inpt signal x1 is supplied to basic circuits 2-0 and 2-1. During T3 period of the clock, operation of a0x2 is performed in the basic circuit 2-0 and the result is added to a2x0 generated by the basic circuit 2-2. Similarly, in the basic circuit 2-1, a1x2 is generated and added to a3x0 generated by the basic circuit 2-3. After clock T4, the result of operation (a0x3+a2x1) is outputted, and this value is added to the result of operation (a1x2+a3x0) stored in a register 13 and output y0 is obtained.
Inventors:
MIURA KENICHI
Application Number:
JP16184882A
Publication Date:
March 26, 1984
Filing Date:
September 17, 1982
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H03H17/00; G06F17/15; H03H17/02; (IPC1-7): H03H17/00
Attorney, Agent or Firm:
Yutaka Morita