PURPOSE: To reduce charge and discharge currents of read buses by enabling all the read buses being accessible during a burst period by a column address of an external input, and by precharging them when a data amplifier is inactive.

CONSTITUTION: A read bus couple ROT/Na is put in a precharged state when a signal DE turns 'L' and a first data amplifier disabled during a period when a data amplifier activation signal DEa is 'H' and when a signal YRD turns 'L' later and precharging is disabled. At the time when an input YON is 'L', an output of an NAND gate NA1 is 'H' even when inputs DEB and YRD are both 'L'. Therefore an output PROa remains 'H' and the read bus couple is kept precharged. Only the read buses being accessible during the burst period are precharged by a signal ENBL being 'H' only during the burst period after input of a read command and by a plate selection signal PDLa. By precharging the fewest necessary read buses, in this way, charge and discharge currents of the read buses are reduced to the utmost.