Title:
【発明の名称】半導体装置
Document Type and Number:
Japanese Patent JP2661318
Kind Code:
B2
Abstract:
Herein disclosed is a bipolar-CMOS semiconductor circuit having a semiconductor substrate, an N- epitaxial layer formed on the semiconductor substrate, an N well formed in the N- epitaxial layer, a P well formed in the N- epitaxial layer, a power supply terminal to which the positive potential is to be supplied, a ground potential terminal, an input terminal, an output terminal, an NPN bipolar transistor formed in the N- epitaxial layer, the NPN bipolar transistor having the N- epitaxial layer as the collector thereof and having an emitter connected to the output terminal, a P-channel type MOS transistor formed in the N well and being connected between the power supply terminal and the base of the NPN bipolar transistor, the gate of the P-channel type MOS transistor being connected to the input terminal, and both the N well for the P-channel type MOS transistor and the N- epitaxial layer as the collector of the NPN bipolar transistor being connected to the power supply terminal, and an N-channel type MOS transistor formed in the P well and being connected between the output terminal and the ground potential terminal, the gate of the N-channel type MOS transistor being connected to the input terminal.
Inventors:
KUMAGAI KOICHI
YOSHIDA TAKETO
YOSHIDA TAKETO
Application Number:
JP7811390A
Publication Date:
October 08, 1997
Filing Date:
March 27, 1990
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
H01L29/73; H01L21/331; H01L21/822; H01L21/8249; H01L27/04; H01L27/06; H01L29/732; (IPC1-7): H01L21/8249; H01L21/331; H01L21/822; H01L27/04; H01L27/06; H01L29/73
Domestic Patent References:
| JP6153762A | ||||
| JP251269A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)