Title:
【発明の名称】半導体装置
Document Type and Number:
Japanese Patent JP3210324
Kind Code:
B2
Abstract:
PURPOSE:To increase a capacity of memory by providing memory cells on the word lines group of one side and also programmable memory cells on the word lines group of another side, and providing protective elements on each bit line existing between these cells. CONSTITUTION:A mask memory cell array MS is constituted in the manner of providing the mask memory cells S1 on each word line WA1, WA2 in the word lines group WA of one side, and a programmable memory cell array PM is constituted in the manner of providing the programmable memory cells SB on each word line WB1, WB2 in the word lines group WB of another side. Thus, the mask memory cell array MS and the programmable memory cell array PM are connected respectively by common bit lines BL, and the protective elements H are provided on each bit line BL existing between the mask memory cell array MS and the programmable memory cell array PM. By this arrangement, a mask ROM, a programmable ROM and the area occupied by these decoder circuits can be reduced, thereby the increase of memory capacity is contrived as much.
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Inventors:
Kenichi Yamakura
Naohiro Sato
Naohiro Sato
Application Number:
JP24957390A
Publication Date:
September 17, 2001
Filing Date:
September 18, 1990
Export Citation:
Assignee:
富士通株式会社
富士通ヴィエルエスアイ株式会社
富士通ヴィエルエスアイ株式会社
International Classes:
G11C17/12; G11C8/00; G11C16/02; G11C16/04; G11C17/00; H01L21/8246; H01L21/8247; H01L27/112; H01L27/115; (IPC1-7): G11C17/12; G11C8/00
Domestic Patent References:
| JP1138688A |
Attorney, Agent or Firm:
Hironobu Onda