Title:
【発明の名称】半導体集積回路装置
Document Type and Number:
Japanese Patent JP2549417
Kind Code:
B2
Abstract:
PURPOSE:To easily and accurately confirm operation characteristics of a logic module, etc., including a sequence circuit by providing a 1st shift register which outputs test data in order and a 2nd shift register which inputs test output signals in order. CONSTITUTION:Multiplexers MX1-MX3 select external input signals supplies through corresponding input terminals I1-Im when a logic module LM1 is in normal operation mode or shift output signals of corresponding input shift registers SR1-SR3 in test mode and send them to a logic circuit LC1. In the test mode, the test output signals outputted by the logic circuit LC1 are inputted to 2nd corresponding shift registers SR4-SR6 and sent to an external testing device through a module bus MB1. Consequently, the dynamic characteristics of the logic module, etc., including the sequence circuit are easily and accurately confirmed.
Inventors:
MYAZAKI KENJI
NAKADA KUNIHIKO
NAKADA KUNIHIKO
Application Number:
JP12382588A
Publication Date:
October 30, 1996
Filing Date:
May 23, 1988
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G01R31/28; H01L21/822; H01L27/04; G01R31/317; (IPC1-7): G01R31/28; H01L21/822; H01L27/04
Domestic Patent References:
| JP626323A | ||||
| JP6077518A |
Attorney, Agent or Firm:
Shizuyo Tamamura (1 person outside)