Title:
【発明の名称】半導体集積回路装置及びその設計方法
Document Type and Number:
Japanese Patent JP3119631
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To equalize relative layout structure by making the length of each I/O cell array being the target of common drawing out the same as the band pitch of a flip chip, and arranging pads on the intersecting points of the center lines of I/O cell arrays and for outside the intersecting points, by the number required for drawing out, on the pitches at equal intervals. SOLUTION: A plurality of I/O cells 2 are arranged at the periphery of an LSI chip 1, and in the inner region 3 surrounded by the I/O cells, a block, which materializes a desired function, is constituted. A corner cell 4 which serves for power is arranged at each corner. Furthermore, pads 5 are arranged all over the LSI surface which materializes a flip chip, and these are connected electrically with the I/O cell or power or the like in the inner region 3. This way, the number of I/O cells is increased or decreased, according to the chip size, and it is put in the relatively same layout at the corner, whereby there is no necessity to prepare special layout for a flip chip, with many kinds of chip sizes provided by ASIC. Moreover, an art work can be used in common, and the design errors can be reduced.
Inventors:
Kazuo Takamori
Application Number:
JP26984898A
Publication Date:
December 25, 2000
Filing Date:
September 24, 1998
Export Citation:
Assignee:
NEC IC Microcomputer System Co., Ltd.
International Classes:
G06F17/50; H01L21/60; H01L21/82; (IPC1-7): H01L21/82; G06F17/50; H01L21/60
Domestic Patent References:
| JP9330934A |
Attorney, Agent or Firm:
Johei Yamashita