【発明の名称】半導体メモリ装置 - INTAANASHONARU BIJINESU MASHIINZU CORP

Title:

【発明の名称】半導体メモリ装置

Document Type and Number:

Japanese Patent JP2531780

Kind Code:

B2

Abstract:

Semiconductor memory device and method for implementing wordline redundancy with no access penalty. A redundant word decoder compares an incoming address signal with a list of defective addresses and, in response to the comparison, produces at least one comparison signal to control the propagation of a redundant driver signal along at least one redundant wordline. A main trigger receives the comparison signal and, in response thereto, triggers the firing of a main wordline driver to produce a main driver signal. The main wordline driver and the redundant word decoder are responsive to opposite states of the comparison signal, such that, for a given comparison signal, only one of the main driver signal and redundant driver signal is applied to a memory array.

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Inventors:

KURISUTOFUA HOORU MIRAA
CHAARUZU SUROON PATOON

Application Number:

JP6642689A

Publication Date:

September 04, 1996

Filing Date:

March 20, 1989

Export Citation:

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Assignee:

INTAANASHONARU BIJINESU MASHIINZU CORP

International Classes:

G11C11/413; G11C29/00; G11C29/04; (IPC1-7): G11C29/00; G11C11/413

Domestic Patent References:

JP62134899A

Attorney, Agent or Firm:

Koichi Tonmiya (1 person outside)

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