Title:
【発明の名称】半導体メモリ装置
Document Type and Number:
Japanese Patent JP3039793
Kind Code:
B2
Abstract:
One cell of the first cell group CG and one cell of the second cell group CxG are selected simultaneously in response to address signals A1 and A2; data of these selected cells are amplified by the first and second sense amplifiers SA1 and SA2, respectively as sense outputs dA, d(OVS), dB, d(OVS); these sense outputs are given to a select circuit SEL including output buffer circuits OB; the select circuit outputs any of the first and second sense outputs to an output circuit Q17, Q18 in response to select signals O(OVS), O(OVS) applied from an output switch circuit OSW on the basis of a specific address signal A12, A12. Since plural sense outputs based upon plural cell data are previously outputted simultaneously from the sense amplifiers to the select circuit and then one of the sense outputs is selected on the basis of a specific address, the cell data can be read at high speed as compared with when data are simply read from cells without simultaneous data transfer and data selection.
Inventors:
Sumako Abe
Youichi Suzuki
Youichi Suzuki
Application Number:
JP17788090A
Publication Date:
May 08, 2000
Filing Date:
July 05, 1990
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G11C11/41; G11C7/10; H01L27/10; (IPC1-7): G11C11/41
Domestic Patent References:
| JP59175094A | ||||
| JP63245020A | ||||
| JP6326891A |
Attorney, Agent or Firm:
Kazuo Sato (3 others)