Title:
【発明の名称】半導体記憶装置
Document Type and Number:
Japanese Patent JP2878713
Kind Code:
B2
Abstract:
A dynamic random access memory has a substrate, plural pairs of parallel bit lines provided on the substrate, parallel word lines insulatively crossing the parallel bit lines to define cross points therebetween, and memory cells provided at the cross points. Each memory cell has a data storage capacitor and a transistor. Sense amplifiers are provided at bit line pairs, respectively, to sense a data voltage. A discharge control section, which is associated with the sense amplifiers, forms discharge paths branched between the bit line pairs and the substrate grounded to progress the discharging of charges, when a certain word line is designated and a memory cell is selected from those memory cells which are connected to the certain word line, whereby the operational speed of the memory is increased.
Inventors:
TSUCHIDA KENJI
OOWAKI YUKITO
TAKASHIMA DAIZABURO
OOWAKI YUKITO
TAKASHIMA DAIZABURO
Application Number:
JP14844889A
Publication Date:
April 05, 1999
Filing Date:
June 13, 1989
Export Citation:
Assignee:
TOSHIBA KK
International Classes:
G11C11/409; G11C11/401; G11C11/4091; G11C11/4094; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): H01L27/108; G11C11/401; G11C11/409; H01L21/8242
Domestic Patent References:
| JP6364695A | ||||
| JP60246092A |
Attorney, Agent or Firm:
Hideaki Tokawa (1 outside)