【発明の名称】半導体記憶装置

Title:

【発明の名称】半導体記憶装置

Document Type and Number:

Japanese Patent JP2938511

Kind Code:

B2

Abstract:

A semiconductor memory device includes a dynamic random access memory (DRAM) cell array (300) as a main memory, a static random access memory (SRAM) cell array (310) as a cache memory, and a content addressable memory (CAM) cell array (320) as a tag memory. The SRAM cell array has word lines (SWL) corresponding in number to match detection lines (23-1 to 23-4) of the CAM cell array. The CAM cell array retrieves contents thereof using external row address as retrieval data. When a match is found in the CAM cell array, a match detection signal is supplied to a match detection line for directly driving a corresponding word line in the SRAM cell array. This semiconductor memory device includes circuitry (22, 22') for generating a cache hit/miss indicating signal in response to signal potentials of the word lines of the SRAM cell array. When the cache hit indicating signal is generated, a column address signal selects a column in the SRAM cell array, and access is made to a memory cell at a crossing between the driven row and selected column of the SRAM cell array. When the cache miss indicating signal is generated, access is made to a memory cell selected by the row address and column address in the DRAM cell array through a column in the SRAM cell array, and in addition data is transferred to a block in the SRAM cell array selected by a block selecting signal from a corresponding block in the DRAM cell array. Further, on a cache miss, data transfer is made prior to external access from a block in the SRAM cell array to a corresponding block in the DRAM cell array.

Inventors:

ARIMOTO KAZUTAMI

Application Number:

JP8705090A

Publication Date:

August 23, 1999

Filing Date:

March 30, 1990

Export Citation:

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