Title:
【発明の名称】半導体記憶装置
Document Type and Number:
Japanese Patent JP3070025
Kind Code:
B2
Abstract:
A semiconductor memory device has a cell and amplifier portion, a syndrome generation circuit, an error checking and correction circuit, and a plurality of memory control blocks. The cell and amplifier portion has a memory cell array, a sense amplifier array, and a column gate array, and each of the memory control blocks has a data bus amplifier, a write amplifier, and a syndrome decoder circuit which decodes syndrome output from the syndrome generation circuit. Consequently, an occupancy area can be reduced by decreasing the number of wiring lines, and a large scale integration and a low power consumption can be realized.
Inventors:
Hiroyoshi Tomita
Application Number:
JP1878492A
Publication Date:
July 24, 2000
Filing Date:
February 04, 1992
Export Citation:
Assignee:
富士通株式会社
International Classes:
G11C11/401; G06F11/10; G11C29/00; G11C29/42; H01L27/10; (IPC1-7): G11C29/00; G11C11/401; H01L27/10
Domestic Patent References:
| JP5771596A | ||||
| JP61278100A | ||||
| JP1133299A |
Attorney, Agent or Firm:
Yasuo Ishikawa