Title:
【発明の名称】シリアル入出力回路
Document Type and Number:
Japanese Patent JP2944084
Kind Code:
B2
Abstract:
In a serial input-output circuit comprising a memory device (15) for memorizing an input serial bit sequence as memorized bit groups, each consisting of a predetermined number of parallel bits, first and second bidirectional shift registers (21, 22) are serially connected through a ring connection (24, 25). A storing arrangement (35-37) is connected to the respective shift registers and directly to the memory device for bit parallel storage of the parallel bits of a selected one of the memorized bit groups in a selected one of the shift registers. An output serial bit sequence is produced from one of the shift registers selectively forwardly and backwardly as regards time relative to the input serial bit sequence. The storing arrangement may comprise a register selector (35) and first and second bit parallel connections (36, 37). The register selector selects the selected shift register and bit parallel loads the selected shift register with the parallel bits of the selected bit group through one of the bit parallel connections that is connected to the selected shift register.
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Inventors:
TODOROKI TOSHA
Application Number:
JP9283188A
Publication Date:
August 30, 1999
Filing Date:
April 14, 1988
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G06F5/00; G06F7/78; H03M9/00; (IPC1-7): G06F5/00
Domestic Patent References:
| JP61236094A | ||||
| JP59177674A | ||||
| JP607678A | ||||
| JP56128751U |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)