Title:
【発明の名称】シリアルワードコンパレータ
Document Type and Number:
Japanese Patent JPH04503742
Kind Code:
A
Abstract:
An apparatus for determining if a received binary word corresponds to the true or complement version of a stored binary word includes means for serially multiplexing the bits of each binary word to the inputs of an exclusive OR gate. The exclusive-OR gate generates a logical high signal each time a mismatch occurs. These signals are applied directly to an error counter and, after inversion, to a match counter. The contents of the error counter and match counter are compared to a stored threshold number. A first signal is generated if the contents of the error counter exceeds the threshold. A second signal is generated if the contents of the match counter exceeds the threshold. Upon the occurrence of both signals, the serial comparison process is terminated.
Inventors:
Elhard, Richard Alexander
Davis, Walter Lee
Herold, Barry Wayne
Davis, Walter Lee
Herold, Barry Wayne
Application Number:
JP50459390A
Publication Date:
July 02, 1992
Filing Date:
January 26, 1990
Export Citation:
Assignee:
MOTOROLA INCORPORATED
International Classes:
G06F7/02; G06F11/00; G06F12/00; H04W88/02; (IPC1-7): H04B7/26
Domestic Patent References:
| JPS63164556A | 1988-07-07 |
Attorney, Agent or Firm:
Shinsuke Onuki (1 person outside)