Title:
【発明の名称】共有バス調停機構
Document Type and Number:
Japanese Patent JP3057934
Kind Code:
B2
Abstract:
A shared bus control system for multiprocessor system having shared buses for a plurality of processors comprises a bus mediation circuit which outputs the switch control signal to switch accessing to the shared buses by the plurality of processors with synchronizing the system clock and a bus selection circuit which selects the address and data from one processor according to the switch control signal and outputs them to the shared buses. It further comprises a state detection circuit which decodes the bus status signal from the particular processor among the processors and detects the bus state of the particular processor and a clock modulation circuit to modulate the operation clock for the particular processor when the state detection circuit detects the particular bus states.
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Inventors:
Hiromi Suzuki
Application Number:
JP29283592A
Publication Date:
July 04, 2000
Filing Date:
October 30, 1992
Export Citation:
Assignee:
NEC
International Classes:
G06F13/28; G06F13/362; G06F13/42; G06F15/16; G06F15/177; (IPC1-7): G06F13/362; G06F15/16
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)