Title:
【発明の名称】共有バッファ同報制御回路
Document Type and Number:
Japanese Patent JP2970572
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To realize broadcast control in the case of the use of a shared buffer control circuit of an address chain system which can be constituted in a certain circuit scale without an influence upon the number of input/output ports with respect to a shared buffer ATM switch. SOLUTION: When a broadcast cell is inputted, an empty address signal 125 is outputted as a main signal cell write address of a shared buffer, and the empty address signal 125 and broadcast output destination information 127 are held as a pair in a broadcast address register circuit 32 in the order of arrival. In a broadcast setting detection circuit 33, values of write counter circuits 311 to 31N are used as addresses for each port to write the broadcast output destination information 127. At the time of cell read, one port is selected from a read counter circuit in accordance with a read port signal 252 from a shared buffer control circuit 43, and the broadcast setting detection circuit 33 outputs broadcast setting bit stored in this counter value. If this bit indicates that broadcast is set, a broadcast address in the head (the earliest held address) retrieved in the broadcast address register circuit 32 is read out and is outputted as a read address to the shared buffer to read out a broadcast cell.
Inventors:
IMAI KUNIHIRO
Application Number:
JP1772097A
Publication Date:
November 02, 1999
Filing Date:
January 17, 1997
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
H04L12/931; H04L12/28; H04L12/70; H04L12/933; H04Q3/00; (IPC1-7): H04L12/28
Domestic Patent References:
| JP7321815A | ||||
| JP5276189A |
Attorney, Agent or Firm:
Suzuki Yasuo