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Patent Searching and Data


Title:
INTEGRATED CIRCUIT DEVCIE
Document Type and Number:
Japanese Patent JPS60763
Kind Code:
A
Abstract:

PURPOSE: To enable the action of a low temperature test at normal temperature by a method wherein a current source which can reduce an injector current only in test modes is provided in an I2L circuit.

CONSTITUTION: The I2L circuit is so constructed as to supply a current to the bases of a multi-collector transistors 10 and 12 with a substrate as the emitters from a current supply circuit 21 via transistors 9 and 11 of reverse conductivity types and to impress an input signal via terminals 4 and 6. Here, the circuit 21 constitutes a variable current circuit which can take binary current values large and small, having a terminal 22 besides a power source terminal 20. The terminal 22 is put at a low level in normal operation and supplies a normal injector current. On the other hand, the injector current decreases in testing by putting the terminal 22 at a high level, thus becoming under the same condition of current as in the case of low temperature.


Inventors:
SUGAWARA MITSUTOSHI
Application Number:
JP10803883A
Publication Date:
January 05, 1985
Filing Date:
June 16, 1983
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L27/082; H01L21/8226; H01L27/08; (IPC1-7): H01L27/08
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)