PURPOSE: To shorten the time for lowering voltage of a word line from a selecting level to a non-selecting level, while reducing a chip area.

CONSTITUTION: A word line booster circuit 2 is arranged closely to one end of a X decoder 3. A boosting signal line LRA is arranged from one end to the other end of the X decoder 3. A boosting signal RA is supplied from one end of the boosting signal line LRA. A word line lowering circuit 6 which makes a lowering current flow through a ground wiring GND2 is provided closely to the other end of the X decoder 3. Lowered voltage is simultaneously applied to the boosting signal line LRA from one end of the boosting signal line LRA by a lowering section 22 in the word line boosting circuit 2 through a ground wiring GND1 and from the other end of the boosting signal line by the word line lowering circuit 6 through the ground wiring GND2.