PURPOSE: To attain multiplex separation while synchronizing at a low-order group at the reception side by adding a different frame pattern to each of n-set of signals applied with m-multiplexing to a digital signal and transmitting the result after applying it with n-multiplexing.
CONSTITUTION: An output signal of an oscillator 3 in a frequency fh" is counted by a counter CTR4, a count signal in a frequency fm' is counted by a CTR5, a clock for multiplexing is fed respectively to multiplex sections MUXA∼MUXC and a clock generating different frame patterns F1∼F3 is fed to frame pattern generators FPGA∼FPGC. The m-set of digital signals respectively are multiplexed by the MUXA∼MUXB and the patterns F1∼F3 are added, which are fed to a multiplex section MUX3, where the signals are subject to m×n multiplex by the clock from the CTR. At the reception, the signal from the multiplex separating section DMUX3 is separated in parallel to frame synchronizing circuits FSYA∼FSYC, where the patterns F1∼F3 are detected, the signals are synchronized in the stage of n-set of the multiplex separating sections DMUXA ∼DMUXC and separated into m-set of signals.
FUKUSHIMA TAKEO
WAKABAYASHI TAKASHI
FURUKAWA TAKAHIRO
FUJIKURA YASUHIRO
| JPS5346216A | 1978-04-25 | |||
| JPS54102817A | 1979-08-13 |