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Patent Searching and Data


Title:
POLISHING CONTROLLER
Document Type and Number:
Japanese Patent JPH0614381
Kind Code:
A
Abstract:

PURPOSE: To self-monitor a state of a count memory system, and to generate an alarm at the time when abnormality is generated by allowing an input to branch, detecting a designated VPI and counting the number of cells in a monitoring period of an input cell, and comparing it with the cell count number corresponding to an item of a VPI of a count memory in a polishing circuit.

CONSTITUTION: When an input cell is a cell of a designated VPI number, a designated VPI detecting circuit 12 informs it to a cell counting circuit 13. Whenever this notice is received, the cell counting circuit 13 adds a cell count value by '1' each, and counts the number of arrival of a designated cell from a start of an operation. The cell counting circuit 13 informs a comparing circuit 15 of cell count information of the present state by a monitoring period lapse instruction of a monitoring period timer 14. The comparing circuit 15 compares the contents of a count memory 10 of a polishing circuit 100, and an output of the cell counting circuit 13, and in the case of noncoincidence, the content of the count memory 10 in the designated VPI is decided to be abnormal and a count memory abnormality informing signal is outputted to an alarm terminal.


Inventors:
NISHIHARA MOTOO
KURANO TAKANORI
YAMANAKA NAOAKI
SATO YOICHI
Application Number:
JP4751293A
Publication Date:
January 21, 1994
Filing Date:
February 10, 1993
Export Citation:
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Assignee:
NEC CORP
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H04Q11/04; H04L12/26; H04L12/28; (IPC1-7): H04Q11/04; H04L12/48
Attorney, Agent or Firm:
Masahiro Fukuyama