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Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS6010765
Kind Code:
A
Abstract:

PURPOSE: To improve resistance against the electrostatic breakdown of both high voltage and low voltage by mounting a protective circuit consisting of a first impurity diffusion region deeper than an impurity diffusion region for an internal element and a second impurity region formed in depth shallower than the first impurity diffusion region between connecting sections to a gate electrode for the internal element from an input and output pad.

CONSTITUTION: A first diffusion region 16 deeper than a diffusion region 15 is formed between junction sections to a gate electrode 14 for an internal element 13 from an input and output pad 12 in an input section 11 to a semiconductor device with the shallow junction section, and a protective circuit element 18 with a second diffusion region 17 in depth in the same extent as the diffusion region 15 is formed. Consequently, an application to the gate 14 of the voltage of static electricity, etc. is prevented. In an output circuit section 21, on the other hand, a first diffusion region 22 deeper than a diffusion region for an output element is shaped between connecting sections to the diffusion region for the output element from the input and output pad 12, and a protective circuit element 24 with a second diffusion region 23 in depth in the same extent as the diffusion region 22 is formed. Accordingly, the junction breakdown of the output element is prevented from voltage generated from noises, etc.


Inventors:
SHIRATO TAKEHIDE
Application Number:
JP11908383A
Publication Date:
January 19, 1985
Filing Date:
June 30, 1983
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L27/04; G02B26/10; H01L21/822; H01L23/60; H01L27/02; H01L29/78; (IPC1-7): H01L27/04; H01L29/78
Domestic Patent References:
JPS5392675A1978-08-14
JPS5694664A1981-07-31
Attorney, Agent or Firm:
Motoki Hisagi (1 outside)



 
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