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Title:
POWER SOURCE CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS5856114
Kind Code:
A
Abstract:

PURPOSE: To monitor a powering-up and a powering-down point in local state, by allowing a system power source device side to monitor remote/local switching on each power source control side without masking a local signal.

CONSTITUTION: When the power source of a UPC or a power source control part PPC is turned on locally, a switch 12 is turned on temporarily to output 1 from an inverter I2 only for the period. When the power source is turned on, on the other hand, a switch 13 is turned on temporarily to output 1 from an inverter I3 only for the period, and their outputs are applied through an OR gate OR2 to an AND gate A, which generates an output 1. This is transferred to an SPC side 20 through the signal line between the UPC and a system power control SPC. The output sets a flip-flop (latch) FF1 in the SPC20, and the output IRQ of an OR gate OR1 goes up to 1, thus causing an interruption. Once this interruption is detected, the circuit resets (RST) the flip-flop FF1.


Inventors:
KANO TAKANOBU
Application Number:
JP15540981A
Publication Date:
April 02, 1983
Filing Date:
September 30, 1981
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H02J1/00; G06F1/26; H02J13/00; (IPC1-7): H04L11/00
Attorney, Agent or Firm:
Minoru Aoyagi



 
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