PURPOSE: To improve the using efficiency of an ROM for parity data, by storing a parity 1-bit corresponding to the data of each address successively from the lower-order bit of a low-order address.
CONSTITUTION: Parity data P0WPn are stored in a 4-bit ROM 11 for parity data an the output terminals D0WD3 of the ROM 11 are connected to the input terminals AWD of a data switching circuit. Address signals A0, A1 are supplied to the data switching circuit and address signals AiWA2 are inputted to the ROM 11. When address "0" is read out to a 8-bit ROM 10 for data, the parity data P0WP3 of the address "0" are read out from the ROM 11 because all the address signals AiWA0 are "0", and inputted to the input terminals AWD of the data switching circuit. Since the address signals A0, A1 of the ROM 11 are also "0", the terminal A of the switching circuit is selected and P0 is outputted as a parity data.
NISHIYAMA NORIKAZU
MORIYA SUSUMU
| JP53099938B | ||||
| JPS5392633A | 1978-08-14 | |||
| JPS5456334A | 1979-05-07 |