PURPOSE: To contrive to improve the integration degree by a method wherein the titled cell is constructed of a select transistor and a floating gate transistor whose control gate is connected to the source of the select transistor.

CONSTITUTION: A bit line BO is connected to the drain of the selece transistor TR21, and a bit line B1 is connected to the drain of the floating transistor TR22. Besides, the bit line B1 is connected to the drain of the TR22, and a word line WL is connected to the gate of the TR21. Further, the source of the TR21 is connected to the control gate of the TR22, and the source of the TR22 is connected to a reference power source VSS. In the layout of the memory cell of this construction, the control gate of the TR22 is a region 36. Such a formation of the control gate of th TR22 as the region 36 enables to make an extremely thin oxide film between the control gate 36 of the TR22 and the floating gate 33, and then to increase the capacitance value. Therefore, the cell area can be reduced.