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Title:
PREPARATION OF COMPLEMENTARY SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS5857745
Kind Code:
A
Abstract:

PURPOSE: To obtain a minute complementary metal oxide semiconductor (CMOS) device by forming isolatedly the epitaxial layers through self-alignment manner in the form of island in such a method as partly including the surface of amorphous dielectric material on the single crystal Si substrate.

CONSTITUTION: The thermal oxide film 42 on the n type Si substrate 41 is selectively removed, and the smooth n type single crystal Si 43 is formed over the substrate at 950∼1,100°C with a pressure of 80Torr using H2 as the carrier and SiH2Cl2. After the oxide film 44 is formed, the p well 45 is formed selectively by the ordinary method, then the oxide film 46 is newly formed, the n well is then formed, and threshold voltages of these are respectively adjusted. Next, the phosphorus (P) additive poly-Si gate electrode 47 is formed and the n layer 49, p layer 50 are formed by the ion implantation selectively using the resist mask 48. After the appealing, such layers are covered with the phospho-silicate glass (PSG), the Al electrode 52 is provided and the Al-Si alloy is obtained under the H2 atmosphere, thus completing a device. According to this structure, a minute CMOS device can be obtained which remarkably reduces diffusion capacitance and moreover prevents existence of single- and poly-crystal transitional regions.


Inventors:
ENDOU NOBUHIRO
KUROKI YUKINORI
TANNO YUKINOBU
Application Number:
JP15668381A
Publication Date:
April 06, 1983
Filing Date:
October 01, 1981
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L27/08; H01L21/20; H01L21/762; H01L29/06; H01L29/78; (IPC1-7): H01L27/08; H01L29/78
Domestic Patent References:
JPS556831A1980-01-18
JPS4944554A1974-04-26
JP44013098A
Attorney, Agent or Firm:
Uchihara Shin