Title:
BOOSTING CIRCUIT
Document Type and Number:
Japanese Patent JPS5829371
Kind Code:
A
Abstract:
PURPOSE:To reduce the number of elements required for obtaining desired voltage value by using one channel electrode as the node of a FET for converting a level and a capacitor, ON-OFF signals as a gate electrode and the other channel as output. CONSTITUTION:Voltage boosted by the first boosting circuit 1 is applied to a circuit block 2, and the capacitor 32 is charged at polarity shown in the figure. Accordingly, a -phi singal is shifted to potential higher by 4V and reaches a -phi1 signal in the gate signals of an FET 25, the FETS 25, 26 are alternately at ON- OFF by the -phi signal and the -phi1 signal, and a phi2 signal is formed. An inverter 38 forms a -phi2 signal, and the phi2, -phi2 signals reach 5V, and are applied to the second boosting circuit 3.
Inventors:
MOROKAWA SHIGERU
SEKIYA FUKUO
SEKIYA FUKUO
Application Number:
JP12867582A
Publication Date:
February 21, 1983
Filing Date:
July 23, 1982
Export Citation:
Assignee:
CITIZEN WATCH CO LTD
International Classes:
H02M3/07; H02M3/06; (IPC1-7): H02M3/06