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Title:
ZENER DIODE
Document Type and Number:
Japanese Patent JPS5835984
Kind Code:
A
Abstract:

PURPOSE: To stabilize Zener voltage, and to reduce cost by forming a deep P type auxiliary layer, which has dielectric resistance higher than a P+ Si layer, into the P+ Si layer, coating a shallow P layer outside the auxiliary layer and the fringe section with SiO2 and shaping an electrode, the principal ingredient thereof is gold, onto the auxiliary layer and the SiO2.

CONSTITUTION: An extremely shallow P+ layer 3 is shaped circularly to an N++ epitaxial layer 1 on an N+ type Si substrate 2. A P type guard ring 4 is formed to the fringe of the P+ layer 3. The four P type auxiliary layers 12 are molded into the layer 3 in depth far deeper than the layer 3, the distribution of impurity concentration is made gentle in the depth direction, and dielectric resistance is made larger than a shallow junction section. The surface is coated selectively with an SiO2 5 including the boundary of shallow and deep junctions, an Au electrode 13 containing Ga is formed and ohmic property is improved, and an Ag layer 13 and an Ag bump electrode 9 are stacked. When normalcy, currents flow through the shallow P-N junction and desired Zener voltage is obtained, when surge, large currents flow through the deep junction and do not break through the junction because the junction is deep even when an Au-Si eutectic is generated. According to this constitution, Zener voltage is stabilized, and yield is also improved.


Inventors:
FUJII HIDEHARU
YAMADA KOUHEI
Application Number:
JP13408581A
Publication Date:
March 02, 1983
Filing Date:
August 28, 1981
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L29/866; (IPC1-7): H01L29/90
Domestic Patent References:
JPS57169265A1982-10-18
Attorney, Agent or Firm:
Toshiyuki Usuda