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Title:
DETECTOR FOR PEAK VALUE
Document Type and Number:
Japanese Patent JPS5917116
Kind Code:
A
Abstract:

PURPOSE: To detect the output peak value of a photodetector which receives the influence of a clock for read out or the through-rate of an electric charge amplifier in a signal processor for a multi-channel photodetector, by providing an analog gate element, a peak holding element and a delay element.

CONSTITUTION: The output current 47 from a photodetector 41 is converted to a voltage signal 48 with an eletric charger amplifier 42. Since the voltage signal 48 proportional to the quantity of light appears at a time t1, the gate of an analog gate element 43 is opened at the time t0' before t1 to allow the passage of the signal 48. The clock signal 49 from a clock generator 46 is directly applied to the photodetector 41, from which the current 47 is read out; at the same time, said signal is passed through a delay circuit 45 by which the gate signal of the element 43 at the time t0' is obtd. The voltage signal past the element 43 is impressed to a peak holding element 44 to hold the peak value. As a result, the peak value of the output signal from the multichannel photodetector subjected to the influence of the digital clock for read out or the through-rate of the change amplifier is detected with good accuracy.


Inventors:
KANAMORI TAKAHIRO
ABE MITSUJI
NISHI MASATSUGU
Application Number:
JP12579682A
Publication Date:
January 28, 1984
Filing Date:
July 21, 1982
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G01J1/44; (IPC1-7): G01J1/44
Attorney, Agent or Firm:
Akio Takahashi



 
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