Title:
TRANSMITTER OF DIGITAL SIGNAL
Document Type and Number:
Japanese Patent JPS6055556
Kind Code:
A
Abstract:
PURPOSE:To reduce erroneous identification when a PCM signal is demodulated by limiting a period when a sag is produced within a period of the PCM signal which is added to the head of a burst mode PCM signal through a lowband cutoff circuit and transmitting a normal signal only. CONSTITUTION:An input signal A is converted into a PCM signal B' by a PCM signal processor 11. In a clock run-in period of the signal B', the clock run-in signals are added longer by DELTAT11 than the conventional time as shown by a magnified figure. Then the signal B' is supplied to a low band cutoff circuit 20, and an M signal K is outputted. The cutoff frequency of the circuit 20 is limited within a range where the signal B' has no deterioration due to the interference between codes. Thus no effect of a sag is exerted on a clock run-in period T11, a dither period T12 and a post-amble period T13 respectively by increasing the period DELTAT11 compared with a time constant which is adversely proportional to the breaking frequency. Therefore the transient response time producing a sag is limited within DELTAT11 even though the signal K is transmitted through a capacitor 30. As a result, a signal C' has no change of the DC component within the desired periods T11, T12 and T13 respectively.
Inventors:
OWASHI HITOAKI
WATAYA YOSHIZUMI
WATAYA YOSHIZUMI
Application Number:
JP16184483A
Publication Date:
March 30, 1985
Filing Date:
September 05, 1983
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G11B20/10; (IPC1-7): G11B20/10
Attorney, Agent or Firm:
Akio Takahashi